Ferroelectric materials are composed of many randomly-distributed permanently polarized regions. Under the presence of an electric field, the regions with a polarization component in the direction of the electric field grow at the expense of the non-aligned regions so that a net polarization can result. If the electric field decreases, the polarization also decreases but at a slower rate so that even when the electric field becomes zero, a remnant polarization remains. A negative coercive field is required to bring the polarization to zero. This hysteresis behavior of a ferroelectric material is the basis of ferroelectric nonvolatile memory devices.
Currently there are two types of ferroelectric nonvolatile memory devices: ferroelectric capacitor which uses a transistor to detect the polarization of a ferroelectric capacitor, and ferroelectric transistor which detects a change in the transistor conductance caused by the polarization of a ferroelectric gate material. The ferroelectric transistor is much more advantageous than the ferroelectric capacitor due to the smaller surface area which enables higher density memory chip, and the non-destructive readout which significantly reduces the fatigue problem.
The ferroelectric transistor is typically a ferroelectric-gate-controlled semiconductor field-effect transistor (FET), which employs a ferroelectric film in the gate stack of the FET, and in which a proper polarization of the ferroelectric film can create an inversion layer in the channel region of the transistor. The basic ferroelectric-gate controlled field-effect transistor is a metal-ferroelectric silicon (MFS) FET. The term MFS represents the layers in the gate stack of the ferroelectric transistor. Thus the gate stack of the MFS transistor consists of a metal (M) gate electrode disposed on a ferroelectric (F) gate dielectric on the silicon (S) channel of the transistor. FIG. 1 shows the schematic of an n-channel MFS transistor. A ferroelectric film 12 is formed as a gate insulating film on a p-type silicon substrate 13, together with source 14 and drain 15 regions having a high concentration of n-type impurity ions. A metal gate electrode 11 is formed over the ferroelectric film 12. The MFS transistor is isolated by the isolation trenches 16.
However, effective transistor operation of the above MFS transistor is difficult to achieve due to the requirement of the ferroelectric/silicon interface. When a ferroelectric film is deposited directly on the silicon substrate, metals and oxygen from the ferroelectric layer may diffuse into the ferroelectric-silicon interface, creating interface trapped charges which affect the polarization of the ferroelectric film, and overall may make the operation of the ferroelectric transistor unstable. Further, since the thermal expansion coefficient and lattice structure of a ferroelectric film is not compatible with silicon, it is very difficult to form a high-quality ferroelectric film with a clean interface directly on the silicon substrate.
To address the drawbacks posed by the direct ferroelectric/silicon interface, a gate dielectric can be inserted between the ferroelectric film and the silicon substrate. The ferroelectric transistor is then called metal-ferroelectric-oxide (or insulator) silicon (MFOS or MFIS) FET. FIG. 2A shows a MFOS memory transistor using a gate oxide layer 27 formed between the silicon substrate 13 and the ferroelectric film 12. Alternatively, a metal floating gate layer 28 can be added between the ferroelectric film 12 and the gate oxide layer 27 as shown in FIG. 2B for a metal-ferroelectric-metal-oxide (or insulator) silicon (MFMOS or MFMIS) transistor. A suitable conducting material (e.g. Pt or Ir) is normally selected for the floating gate 28 to allow the deposition of the ferroelectric thin film and to prevent diffusion of the ferroelectric material into the gate dielectric and the channel. The floating gate layer 28 is also called bottom electrode, or bottom gate, in reference to the other gate electrode 11, called top electrode, or top gate.
Such gate stack structures (metal-ferroelectric-oxide gate stack or metal-ferroelectric-metal-oxide gate stack) overcome the surface interface and surface state issues of a ferroelectric layer in contact with the silicon substrate. However, they incorporate other difficulties such as higher operation voltage and trapped charges in the bottom floating gate layer. The operation voltage of these transistors is higher than the ferroelectric layer programming voltage by an amount of the voltage across the gate dielectric. And when there is a voltage applied across the ferroelectric thin film, there will be current flow in the gate stack, and charges would be trapped in this floating electrode. The trapped charges may neutralize the polarization charges at the interface of the bottom electrode and the ferroelectric film and could shorten the memory retention time of this structure.
Various prior designs have been disclosed to compensate for the trapped charges in the floating bottom electrode. One of the prior art design to reduce the trapped charges in the lower electrode is the formation of a Schottky diode such as a metal-ferroelectric-metal silicon (MFMS) device disclosed in Nakao et al., U.S. Pat. No. 5,303,182, entitled “Nonvolatile semiconductor memory utilizing a ferroelectric film”. A Schottky barrier is formed between the bottom metal electrode of the gate unit (or a very shallow junction layer) and the silicon substrate. The Schottky ferroelectric gate memory transistor requires a space between the bottom electrode and the source and drain region or a very shallow n-channel under the gate, therefore the drive current of the Schottky ferroelectric gate memory transistor can be relatively low. Hsu et al., U.S. Pat. No. 5,731,608, entittled “One transistor ferroelectric memory cell and method of making the same”, and its continuations and divisions (U.S. Pat. Nos. 5,962,884; 6,117,691; 6,018,171; 5,942,776; 5,932,904; 6,146,904; 6,011,285; 6,531,325), hereby incorporated by reference, disclose a distance between 50 to 300 nm from the bottom metal electrode to the source and drain to reduce the possible high leakage current due to the increased field intensity at the metal edge of the Schottky diode because of the sharp edge at the periphery of the metal contact. Alternatively, Willer et al., U.S. Pat. No. 6,538,273, entittled “Ferroelectric transistor and method for fabricating it”, discloses a recess of the source and drain below the surface of the semiconductor surface in a Schottky ferroelectric gate memory transistor.
Another design to reduce the trapped charges in the lower electrode is to provide a conduction path for the lower electrode. Black et al., U.S. Pat. No. 6,069,381, entitled “Ferroelectric memory transistor with resistively coupled floating gate” discloses an integrated resistor in the form of a spacer between the bottom floating gate electrode and the source/drain to remove the trapped charges. Moise et al., U.S. Pat. No. 6,225,655 and its continuation U.S. Pat. No. 6,362,499, entitled “Ferroelectric transistors using thin film semiconductor gate electrodes” disclose an external resistor connecting the lower electrode to ground to drain the trapped charges. This additional resistor ensures that the potential of the floating gate will approach that of the source/drain region after a certain delay time, but this could affect the high speed switching characteristic of the ferroelectric memory. Yoo, U.S. Pat. No. 5,812,442, entitled “Ferroelectric memory using leakage current and multi-numerical system ferroelectric memory” discloses a leakage gate dielectric to remove the trapped charges through the silicon channel. The leakage current is generated by a Schottky emission or a Frankel-Poole emission or Fowler-Nordheim tunneling to reduce the bound charges in the bottom metal electrode.